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The Challenges and merits of Analog/mixed-sign and RF gadget Verification above the Transistor degree | L50-503 practice questions and Real test Questions

utility examples using tools that emphasise graphical capture and exploration.

Andrew ok. Betts, Daniel Saias, Hervé Guegan, Nicolas DelormeAsygn, France

abstract— nowadays’s on-chip Analog/mixed-sign and RF (A/RF) systems have reached a limit of dimension and complexity the place transistor-stage SPICE and FastSPICE simulation approaches can not carry a verification solution on time.  Challenges encompass, of direction, circuit dimension, however additionally the heterogeneous nature of the A/RF methods, their architectural complexity (e.g. modulation schemes, analog/digital mix, in-built configuration, calibration and compensation schemes), and traumatic standards (e.g. high Q, repeated sub-blocks).  Such challenges can simplest be surmounted by way of relocating to a stage of abstraction above that of the transistor [Chang].  They trust how this can be achieved in apply, while preserving the stage of simulation accuracy needed for A/RF verification.  The benefits of this strategy are illustrated with examples in accordance with new tools that work on the Analog gadget Implementation (ASI) degree of abstraction and which desire schematic, as opposed to language-based,  descriptions of the A/RF device.


while tools for analog design are anything but fundamental, and whereas progress is always being made to Strengthen such equipment, the fact remains that they've eluded the stages of automation achieved through their digital counterparts.  The grasp stage of description remains the transistor, and due to this most functional verification efforts are carried out at this stage of abstraction.  contrast this with usual digital methodologies where signoff purposeful verification is performed at RTL stage, relying on appropriate-with the aid of-development methodologies to transition to gates, transistors and layout.

besides the fact that children, the expanding size and complexity of on-chip sub-programs makes it not possible to rely only on SPICE simulation for verifying on-chip A/RF methods [Chang].  for example, the following challenges are becoming greater widely wide-spread and complicated to tackle:

  • Requirement for simulations over many a whole lot of clock or carrier cycles so as to verify suitable stabilisation or setup of blended-signal circuits (e.g. PLL setup, real-time configuration, calibration or compensation of circuit parameters).
  • Requirement to determine the performance of the finished system On Chip (SOC), taking into consideration the non-highest quality habits of A/RF sub-systems.
  • Requirement for yield analysis involving many method and temperature corners, the number of which has increased hugely with the latest technology nodes.
  • deserve to analyse techniques which have very excessive selectivity (Q) and/or an incredible unfold in time-constants (e.g. sampled-analog, excessive ratio of carrier to modulation frequency, ..).  These circuit characteristics extend simulation runtimes significantly.
  • need for “what if” analysis all the way in the course of the move, from A/RF gadget specification via to silicon verify (to facilitate debug projects).
  • One approach to these issues is to make use of a FastSpice simulator (e.g. [Takao]).  These simulators obtain shorter runtimes than SPICE via computerized simplification of transistor fashions and, probably, via partitioning the circuit into sections for which sub-simulations could be run in parallel.  The fundamental dangers of this method are (1) the time and trouble required to set the various parameters that manage the simulation manner, including the degree of transistor mannequin simplification, (2) the steadiness and accuracy of the ultimate consequences.  truly, it is possible to acquire FastSpice consequences that aren't most effective of low precision, however really false.

    A 2nd method, which looks to becoming everyday with SOC teams, is to use a language corresponding to Verilog-AMS or VHDL-A to jot down behavioral fashions of A/RF sub-techniques [Muhammad][Peralias][Wang].  This system has the appreciable benefit of elevating the abstraction degree of simulation above the transistor degree, as a result decreasing simulator runtimes by way of a number of orders of magnitude.  Drawbacks consist of the abilities required to write down the behavioral models (the languages are potent, however not trivial to be trained, and terrible code can cause unstable models) and the issue in guaranteeing that these models correspond to the implementation being described.

    There is no “formal” solution to the latter query at latest.  just as they cannot synthesise from larger levels of description all the way down to transistors for analog circuits, so they cannot immediately summary from the transistor stage to better stages, nor can they do equivalence checking between these levels.  in brief, there is not any commonplace, automated solution to those concerns in the A/RF area.  it is for this reason a question of finding the tools and strategies that cut back the chance of human error to an acceptable degree.

    The equipment and components that they describe here work at a degree of abstraction that they have referred to as the Analog equipment Implementation (ASI) degree, to be able to distinguish it from the larger ranges of abstraction which are used, as an example, in specification files and with Matlab [Matlab] and which are strongly equation-primarily based.  

    with a purpose to healthy well with regular apply in A/RF design agencies, their preferred tools want a schematic description of the A/RF sub-systems.  further, manage of the tool and exploration of consequences is viable through use of the graphical interface only.  ultimately, and most vital, these equipment use inherently strong algorithms.  they are in line with fashions that can be proven reliable and, in distinction to FastSpice, automated mannequin simplification isn't used.  If instability or lack of convergence is seen in the simulations, then it's due to a property of the circuit, as opposed to the simulator. Very quickly runtimes are for this reason performed without the drawbacks of FastSpice or language-primarily based options.

    II.    FLOWS

    The fundamental problem in ASI-based verification is the implied deserve to go “bottom-up”.  that's, if the verification simulation problem is handled in isolation, with the task defined as “inputs = transistor netlist + vectors + expected results, output = flow/fail”, then they should by some means determine how to get from the transistor level netlist to the ASI description.  This statement leads us to 2 fundamentally different tactics:

  • ASI-primarily based verification as an isolated task
  • ASI-based mostly verification as a part of a move built to aid this verification trend
  • The method taken will rely upon the assignment in question, and they do not discount both.  while life is generally more at ease if the second approach may also be taken, this means advanced planning and investment that is not always possible.  

    we can supply an instance of the first method, which is more ad-hoc than the 2d, in the next area.  The 2nd strategy begins on the element where a simulatable specification is based for the A/RF system to be carried out, and this strategy is described in [Betts].  in this case, the effect of the ASI-primarily based verification is a great deal less complicated to foretell, for the reason that there's a deliberate continuity from the work of modeling the meant implementation via implementation and meeting of the part blocks/IPs to closing verification of the A/RF subsystem.  due to the fact an ASI-degree model is purchasable all over the procedure, with updates from expertise gained during implementation regularly refining its accuracy, the manner should be a convergent one and the variety of final-minute surprises is decreased.  here diagram summarises the manner:

    III.    EXAMPLES AND benefits

    Our first instance became proven on the ASI stage after the designed become definitely completed at the transistor-stage.

    It consists in a stereo audio DAC IP designed for easy IC level integration of audio techniques. Combining low vigour with high dynamic efficiency, it is naturally supposed for portable and/or stressful functions comparable to MP3 avid gamers, PDAs and mobile phones.

    it's developed around a 32/64/128/256x interpolating digital filter, a third order MASH Sigma Delta modulator and a single stage multi aspect DAC, followed by using a enormously linear line buffer amplifier.

    The totally differential structure of the analogue front-end guarantees a strong immunity to any ordinary mode perturbation when integrated in a noisy ambiance. it's manufactured in ATMEL high-density ordinary 0.13µm CMOS procedure thus providing a cost constructive answer when integrated in a system on Chip (SoC).

    The function “click-less” has been brought with the intention to cut pops and clicks, all over the startup/shut-down phases.

    The circuit’s block diagram is shown below:

    The IP main aspects are as follows:

  • 90dB dynamic latitude
  • eight to 96kHz sampling frequency
  • 10 mW general consumption @ 3V deliver
  • Vector quantized dynamic facets matching (DEM) engine
  • a hundred and twenty to 0dB / 1dB step programmable attenuation
  • De-emphasis filter
  • The cell dimensions are 1mm2 for the analog part and zero.4mm2 for the digital part, representing 46Kgates, decreased to about 1Kgate for simulations of the A/MS a part of the IP.

    As this example falls into the first category outlined before, some translation work needed to be conducted to produce de ASI-level models from the transistor-stage netlist. Analog transistor-degree cells (e.g. opamps, switches, references…) and digital transistor-level gates have been mapped to a group of analog  and digital ASI primitives. because of the particularly hierarchical nature of the design, the usual guide conversion effort become roughly one man-day. This effort is rewarded via some distance when it involves function the verification simulations, as shown in the table below.

    Simulation engine Abstraction degree CPU Time Spice Transistor 80 hours Spice ASI (VerilogA macromodels) 10 hours Asygn tools ( ASI (Asygn primitives) 2 minutes

    With the same abstraction stage (i.e. macromodels), the ASI simulation operating on a tool designed notably for this level of abstraction provides a x300 development in terms of CPU time, while holding the identical degree of accuracy: the following determine indicates how close the simulation effects stay (both plots are just about indistinguishable in B&W!).

    The conclusions of this first instance are:

  • a superb deal of verification insurance can also be executed at very modest funding, even when ASI-primarily based verification has now not been deliberate from the beginning within the global design stream.
  • with ease relocating to the ASI degree of abstraction will provide restrained gains if the simulator used isn't optimised for operation on the level of abstraction.  Specifally, a SPICE-class simulation engine, even when used with ASI-stage macromodels, will run a great deal slower than a purpose-built ASI-stage simulator.
  • Our 2nd instance is certainly one of a gadget for which ASI-stage verification become planned from the starting .

    The Analog/combined-signal (AMS – a subset of A/RF) equipment in query is an imaging array.  a number of hundreds of heaps of pixels, together with their non-most appropriate traits, have to be simulated.  The verification objectives are:

  • To make sure that the array is functionally relevant.
  • To ensure that the device meets specification within the presence of distinct non-most reliable consequences, a few of that are erratically or randomly unfold throughout the pixel array.
  • To be capable of swiftly and visually debug any blunders found.
  • This example is a fine illustration of the issue in adapting well-known tools to particular A/RF systems.  in this case, the huge array of pixels is a big problem to any analog simulator.  This became overcome by adapting and reconfiguring accessories from popular equipment right into a custom setup.  In certain, the pixels within the array were modeled at the ASI stage and then compacted, for quicker simulation.  extra, the simplicity of the pixel models (when compared to commonly encountered analog add-ons akin to amplifiers, oscillators, and so forth) gives us the opportunity to deliver an automatic extraction of the ASI mannequin parameters from SPICE outcomes, accordingly overcoming probably the most predominant barriers in ASI-based verification.  This approach allows the final gadget to achieve “signoff” repute within the sense that regression runs may be automatically run at ASI stage the use of as enter SPICE netlists extracted from design – without any guide intervention.

    A sketch of the device is supplied beneath:

    The verification device is at present purposeful and they are in the process of refining the standard specification-to-tapeout move.  The runtime advancements got through this ASI-primarily based, custom strategy are very considerable, permitting us to examine many forms of non-gold standard phenomena that had been prior to now out of bounds to simulations.  in the past, even the simulation of ideal behavior changed into infeasible on the entire imaging array.

    IV.    tool requirements

    Our event from the verification projects described above, plus many others within the A/RF and digital domains (and even in micromechanical programs) has led us to here hope record for aiding tools:

  • tools should be as integrated as possible into typical A/RF dressmaker environments.  here is not without difficulty a remember of dependancy and luxury, however additionally to stay away from double-entry of suggestions and to minimise the chance of human error in everyday.
  • A corollary to the preceding aspect is that schematic entry need to be used at any place possible, considering this is the preferred approach of shooting circuits of most A/RF designers (as adversarial to writing descriptions the usage of a circuit description language) .
  • besides common batch-style inputs and outputs, equipment need to provide a excessive stage of interactivity, allowing clients to perform dynamic “what-if” type analyses.  This class of performance is greater frequently associated with specification and design, but we've found that it is also fundamental for debug, which represents a huge share of engineering time spent in verification.  once more, if these interactivity facets will also be introduced graphically, so lots the more advantageous.
  • A important factor of the interactive debug undertaking, simply mentioned, is knowing the connection between sign outputs from the circuits below examine and the contributing add-ons (wanted and less welcome) of these indicators.  it's crucial that verification tools allow the breakdown of output alerts into such add-ons.
  • since it is not (yet) viable to automatically abstract from the transistor to the ASI level, an exceptionally vital common reference between both tiers of abstraction is the testbench.  equipment for ASI-degree verification need to for this reason help designers to keep consistent testbenches between the ASI and transistor tiers.

    progress in chip technology and Analog/combined-signal and RF (A/RF) techniques design makes it necessary to advance verification methodologies and equipment that take advantage of the Analog device Implementation (ASI) level of abstraction (i.e. they must circulation above the transistor degree).  There is not any normal formulation or device that may aid this procedure in all circumstances.  every so often it is not even viable to plan an entire specification-to-silicon movement incorporating ASI-level verification, and they have to assume these situations also.  Examples had been given of each deliberate and less deliberate initiatives incorporating ASI-stage verification, illustrating the use of latest equipment which are well tailored to this assignment.  in response to this event they record a few elements (some of that are already carried out in their equipment, others of which are in building) that facilitate ASI-level verification of  A/RF methods.


    [Betts] Betts; Delorme; profiting from the equipment stage in analog design; EETimes; 28 June 2010;

    [Chang]  Chang, H.;   Kundert, ok.; Verification of complicated Analog and RF IC Designs; IEEE proceeding; March 2007;  or

    [Matlab] MathWorks - MATLAB and Simulink for Technical Computing;

    [Muhammad] Muhammad, k. et al;Verification of RF SoCs: RF, analog, baseband and software;

    [Peralías] Peralías, E.; A VHDL-based Methodology for the Design and Verification of Pipeline A/D Converters; DATE 2000 conference; cases/PAPERS/2000/DATE00/PDFFILES/07D_1.PDF

    [Takao] Takao Ito; Analog behavioral models reduce mixed-signal LSI verification time; EETimes; 22 June 2007;  

    [Wang| Wang et al; event pushed Analog Modeling for the Verification of PLL Frequency Synthesisors; BMAS 2009;

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