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IBM V3 test

setting up a Reusable IP Platform inside a device-on-Chip Design Framework targeted against an academic R&D environment | C2140-823 exam questions and exam Cram

by way of Brendan Mullane and Ciaran MacNamee,Circuits and device analysis Centre (CSRC),tuition of Limerick, Limerick, ireland

abstract:

A key challenge facing the semiconductor business is to mix highbrow Property (IP) from quite a lot of sources right away and efficiently. Design times are invariably pressurized with the aid of time to market necessities and extending complexity. Industrial practices for establishing equipment-on-Chip (SoC) IP have developed beneath these pressures, but making use of these practices in an educational ambiance items additional challenges. The theory for developing a framework for producing IP become in accordance with this reuse revolution and the advantages it brings to R&D. The capability to design high excellent IP and to permit work practices for reuse methodology helps to achieve working SoCs in a timely and productive manner. This paper describes a methodology for implementing IP reuse practices suited to an tutorial atmosphere.

1. Introduction

a number of factors are obligatory for efficient IP use, flexibility of integration, more suitable ease-of-use, minimized can charge, and first rate work practices for establishing IP. This paper is in response to specific work constructing an ASIC using 0.35ìm manner technology. The architecture in this IC is corresponding to SoC designs that use an 8-bit CPU and associated peripherals. it's proven that the framework for IP construction centered all through this project can make sure a hit deployment of each present and new designs in future projects.

The latest vogue in SoC design is to make use of present IP as a great deal as viable. IP within the type of CPUs, DSPs and controllers, are being reused in new IC projects at semiconductor methods design houses. Engineering teams now design chips with thousands and thousands of gates in less than a yr. just recently, such productivity would have been unimaginable, even unthinkable with out hardware IP reuse. Most educational environments do not need the components and infrastructure to allow such engineering ability, however the underlying principles of reuse may also be applied to enable greater effective IP era and skills retention for useful R&D.

This paper introduces a group of guidelines and a technique used to be sure a constant method to designing IP and to enable for reuse of these modules in future initiatives. the first stage changed into to investigate optimum industrial practice. Work describing the ASIC construction cycle and its have an impact on on IP era become performed. a group of requisites for guaranteeing IP quality and ease of integration turned into also organized. A key objective became to make certain knowledge can be retained inside the school centre to have in mind expected graduate turnover.

2. IP Reuse Framework in CSRC

A overview of the normal considerations in design use and reuse became initiated [1]. a considerable number of IP standards were reviewed and these protected Freescale’s Semiconductor Reuse standard [2], VSI Alliance’s set of requisites for establishing SoCs [3] and OpenMORE [4]. IP reuse might on no account have happened with out specifications or with out the underlying infrastructure [5]. Design and verification reuse, a fact of lifestyles today for many SoC designs, ensures the productivity gap is stored manageable[6]. Design reuse considered an easy thought that can also be conveniently adopted, has endured to be difficult in observe. issues exist in getting engineers to believe that reusable IP will work anytime it's used in an IC. featuring IP guide capabilities and adoption of a proper verification system develops this have faith.

2.1 SoC structure and Infrastructure

The intention of this assignment became to set up a design methodology for producing IP. The methodology concerned architectural choices and selection of design-flows for IP development accompanied via the prerequisite IC design tools. mission criteria such as the SoC structure, third-birthday celebration core use, in-apartment IP building and the equipment bus interface were all regarded earlier than the IC structure become concluded and the peripheral integration was conducted. The simple SoC architectural diagram is proven in figure 1 and the finished chip become taken through verification and the again-end tiers of synthesis, layout, static timing evaluation and closing design rule checking.

figure 1: SoC Design structure

here key selections were made in relation to the IP guide constitution.

2.1.1 Peripheral Bus Interface

The choice of a typical SoC device bus for connecting the CPU to the equipment peripherals was vital to the goals of this assignment. the use of a standardized bus architecture is elementary to setting up reusable IP. various bus requirements had been investigated for the needs of the CSRC IC tasks. The 8051 CPU became used during this design and besides the fact that children the internal particular function Register (SFR) bus turned into regarded, the authors wished to make use of a typical bus design to be reused in other IC implementations.

most of the fundamental IC and IP companies base their IP portfolio development round a single SoC bus structure. Semiconductor groups similar to ARM and LSI good judgment use the open source AMBATM [7] bus ordinary. IBM makes use of its personal proprietary CoreConnectTM [8] bus commonplace. The OpenCores initiative makes use of the WishboneTM [9] defined bus interface. The authors followed that the AMBA bus architecture was well supported amongst the IP vendor group. This extensive acceptance arises from the provision of an open bus ordinary it is license free and neatly proven in latest SoC designs. customers have a high diploma of self assurance opting for IP it truly is regarded vendor unbiased. moreover, the AMBA bus is neatly supported by EDA organizations providing verification help. The AMBA bus became chosen because the bus interface for CSRC SoC tasks for these causes.

The AMBA bus allows for partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time appropriate system design. It also quickens product migration by helping module reuse. In particular, the AMBA APB bus specifies a versatile interface and small overhead help for low bandwidth peripherals. The IP design using the AMBA interface is made less difficult through partitioning the high-end and low-end devices inside the device and helps power effective designs. the entire peripherals during this design used the AMBA - superior Peripheral Bus (APB) as the standardized interface. The CPU as a single bus grasp become interfaced to all of the peripherals by the use of an in-apartment designed AMBA bridge interface.

The benefits of the usage of a typical bus interface for core construction are well documented [1, 10, 11]. A demo AMBA APB register module, shown in figure 2, become helpful for demonstrating the preferred interface design to postgraduates. The RTL code for this module helped the crew to remember the ideas of good coding follow to consist of parameterization and validated the use of revision manage for code adjustments and malicious program fixes. all the IP developed in this IC challenge can be reused in any other AMBA primarily based SoC purposes and this aids future product and platform building

figure 2: pattern APB module

2.1.2 3rd birthday celebration Core Licensing

another tremendous task was to designate an appropriate microcontroller for the mission. The IP neighborhood turned into approached in regards to licensing of the CPU and debug cores. there have been a few facets to licensing IP cores from an academic perspective. It become essential to be certain a licensing association changed into made the use of a non-business analysis- licensing mannequin. Many companies had been best prepared to license their cores in keeping with a full commercial arrangement and the charges quoted were past an academic research price range. Some vendors were willing to accept as true with a reduced non-commercial license price with the re-introduction of full costs provided the IC proceeds to business application. other IP providers confined their set of deliverables to FPGA netlist implementation best. This constrained their choice of third birthday party CPU and debug cores. happily, some IP agencies had experience dealing with tutorial situations and have been organized to unlock IP deliverables and support for non-industrial analysis pastime at a reduced charge. The main author became in a position to perform a survey of appropriate cores and came to an contract for the 3rd birthday celebration IP necessary for the SoC project.

2.1.three Design Flows

The ASIC design move and electronic Design Automation (EDA) tool alternative is a vital element of a good IP framework. The alternative of tools must complement the design flows and assist reusability of IP. The centre accesses tool units provided as educational programmes from the semiconductor EDA groups. The CSRC also has access to conventional EDA tools by way of the Europractice[12] software service scheme. Their FPGA and Digital design flows had been drawn up around the availability of these tools and to plot the SoC IP development and integration. These flows had been constructive in picking out the diverse stages thinking within the construction of IP and SoC designs. moreover the digital design stream, a flow for FPGA prototyping become also brought. The FPGA construction allows for for an affordable design validation platform and adds confidence through making certain suitable habits before final tape-out.

2.1.three.1 Digital IC Design flow

The digital design follows the basic ASIC implementation route. a couple of semiconductor company sites and technical paper searches printed the normal design circulate that exists for digital ASIC design [13], [14].

figure three: Digital IC design circulation

The design circulation and tools preference as drawn up in determine three have been tailored to tool availability and the choice of IC procedures provided by Europractice.

2.1.3.2 FPGA Design circulate

The FPGA move in figure four is very comparable to the digital IC design circulate, but the design equipment to enforce and software a FPGA design are distinct. The challenge used the Xilinx design kits and tools made available via the Xilinx university Programme. They used Xilinx Spartan 2 and 3 boards to put in force the digital design facets. The Xilinx ISE webpack is a group of tools that takes Verilog RTL code and runs it via synthesis, real design to gadget configuration. The last bit file can then be downloaded to program the FPGA equipment to verify the practical behavior of the digital design. FPGA verification suggestions and their importance in design validation and reuse are discussed later.

figure 4: FPGA Design movement

2.2 CAD Infrastructure

The CAD infrastructure turned into more suitable to carry out SoC development inside the centre. The normal constitution covered 3 low-grade UNIX servers for running the IC design tools and maintaining mission statistics. A plan became initiated to Excellerate the IT hardware wants. every of the person PCs had been put in with VMware Linux, permitting clients to keep their home windows OS but more importantly each and every workstation might use its own CPU processing vigour with Linux to carry superior performance. Two high vigour Linux mainframes, received for retaining the challenge databases were additionally utilized as license servers for the supported EDA tools. the new set-up gives the performance requirements to carry out IC R&D in the CSRC centre.

one more step changed into picking the EDA equipment integral for IP development. equipment for verification and guaranteeing best of RTL code have been no longer in region. besides the fact that children using their Europractice membership, the centre had access to customary EDA equipment at a decreased cost. equipment corresponding to ModelSim for RTL verification and Leda for RTL analysis have been bought. The newest edition of Design Compiler changed into also upgraded according to business necessities.

3. Design Methodology and IP reuse Implementation

application of reuse can pay off when it comes to building charge and time-to-market. This area summarizes the development milestones for a typical IP design. Defining the flow and linked design reports helps assure a repeatable, high excellent, and reusable block of peripheral IP. a different improvement of a documented move is that other design businesses can use this methodology to boost IP in an analogous method; ensuring IP is consistent in its implementation, integration movement, deliverables, and usual fine.

3.1 development Milestones

IP/SoC design milestones are crucial to the birth of working silicon and attaining a ‘right first time’ policy. These milestones are markers placed down right through the development phase to manipulate and measure the design recreation and development. These markers indicate reviews happening right through the vital tiers of the design section from beginning to conclusion. Milestones take area at the natural development of the project. determine 5 and desk 1 describe the sign-off milestones to consist of all predominant design reports.

determine 5: IP development Milestones

table 1: IP development stages

degreeReview Description FSR functional Spec evaluation practical specification is finished, details on effort estimation, work breakdown structure and agenda. DSR Design beginning overview Design start, practising, RTL coding & synthesis guidelinesTPR check Plan assessment finished specification of verification ambiance, test instances, bus-fashions, transactors. RCR RTL Code overview RTL bug fixes recognized through exhaustive verification & RTL Lint/code checking TLR Trial layout assessment establish floorplan and perform P&R. Floorplan in accordance with module connectivity, resolve congestion and timing –analyze clocking FVR remaining Verification assessment high precedence testing completed. widespread bugs within the RTL are fastened. coverage analyzed. Low precedence trying out good enough. FDR last Design review assessment integrity assessments (DRC, LVS) STA, check Vectors and final gate-level verification with comprehensive layout timing.

three.2 mission Database constitution

A standardized directory constitution is a must-have for IP reusability. an effective and simple to make use of database constitution ensures compatibility and consistency of peripheral design. IP development comprises specification, coding and verification as key design degrees. consequently, many guide file codecs are required. IP preservation is also a key theory in IP reuse. The means to log and retain song of design changes is vital to the normal best of the design. determine 6 indicates the CSRC listing structure to guide the IP building tiers.

determine 6: normal CSRC listing Database

3.three. Reuse instructions

3.3.1 Specification stories

The design reports are enormous in terms of generating a framework for IP development and reuse. These stories support documentation and ensure decent design practices.

three.3.2 practical Specification

This document gives a detailed functional description of the module and is written in advance of the IP building. The FSR review takes region to be sure all points of the peripheral functionality are covered. The specification can be used to delivery the design and RTL coding. The purposeful specification has to be up to date for this reason with any further features requirements. The CSRC makes use of a draft template doc as a guideline for producing useful block and IC design standards.

three.three.three RTL Coding and analysis

RTL building involves coding the peripheral in a hardware description language such as Verilog or VHDL. Verilog RTL turned into used and a group of coding instructions for the IP technology become issued. This set of coding concepts ensures consistency, coding fashion satisfactory and provides for greater protection. The RCR is a high degree overview of the RTL code to make certain it's stylistically correct and maintainable. The intent is to double-assess the code exceptional. The basis for this evaluation is the RCR guidelines. RTL analysis is performed the usage of Leda for crosschecking RTL code guidelines against the Reuse Methodology manual (RMM). initial FPGA/IC synthesis can even be used to spotlight any RTL concerns with regard to synthesis.

3.3.4 Revision handle

Revision control is imperative to the conception of design reuse and ensures important information isn't lost during the design part. Revision handle and file management is above all vital all over RTL coding as any code misplaced right through this stage can seriously have an effect on the standard design timeline. To aid manipulate info, engineers use supply control management systems. These are usually bundled with the Linux working methods or purchasable from GNU (RCS, CVS, Subversion). These code management methods provide a complete history of each file as separate models.

3.three.5 malicious program renovation

dealing with bugs is an important consideration for any design framework. it's average to locate practical irregularities within the design and their incidence does not mirror the expertise of hardware designers. once a problem is identified, it needs to be resolved. All design groups want a technique for monitoring considerations and ensuring their resolution. The authors proposed maintaining a bug file for any design connected concerns.

3.four Verification and Validation environment

The verification section is critical to providing first time working silicon. Their verification methodology makes use of a twin song strategy. Verification occurs on the module level and also on the SoC device stage. The Module Verification atmosphere (MVE) functionally validates the core and ensures all design traits were comprehensively confirmed. The SoC Verification ambiance (SVE) checks the cores’ conduct at the system degree and in selected assessments the connectivity between the core interfaces. An FPGA/ASIC design verification approach changed into used to validate the undertaking at the equipment SoC level.

3.4.1 Module Verification atmosphere (MVE)

a vital a part of the MVE became the technology of the APB Bus functional mannequin (BFM) to generate the purposeful behavior of the system bus. the entire peripherals were in response to this standardized bus architecture and this enabled using a regularly occurring model to check the bus interface and registers contained in the peripherals. This model additional provided a simple to use verify atmosphere. The diagram in figure 7 illustrates this. The BFM utilized Verilog initiatives for study/write accesses, including wait state manage and become reused in all of the peripheral examine environments. The BFM changed into positive for running assessments to obtain self assurance within the functional conduct and for focused on high code insurance.

figure 7: APB Bus functional mannequin

three.four.2 SoC Verification ambiance (SVE)

The SVE consisted of a separate but similar verify answer for FPGA prototyping and the ASIC equipment level verification. The FPGA solution changed into advantageous for mapping the comprehensive SoC RTL code to include the CPU, debugger and all of the peripherals onto a FPGA. determine eight illustrates the basic structure implemented onto the FPGA device.

determine 8: FPGA Prototype Validation

The CPU and different leading peripherals are related together as a single platform and checks were developed in R8051 CPU core application code to function the peripheral assessments. The ASIC verification environment is comparable to the FPGA examine bed, except during this case all checks had been run the use of RTL and process specific gate-level stimulations. each and every of the peripheral firmware exams developed for the FPGA prototyping have been reused at ASIC device level.

four. results and Conclusions

The assignment goal become to enforce a SoC design framework for the delivery of reusable IP. The chosen standard system bus aided the development of plug and play peripherals that will also be reused in lots of different SoC purposes. The development of the 8051 CPU exterior records bus to equipment bus-bridge provided for a standardized interface and simplified the peripheral construction.

The design flows of Figures four and 5 had been adopted to be certain a constant design approach for the building and equivalent help for business usual EDA tools. The directory constitution as defined in area three.2 turned into additionally crucial for associating information with every stage of the IC building and conserving a neatly-managed database. every of the implemented IP blocks follows this regularly occurring database constitution and this ensures reusability going forward. Design stories ensured self assurance and great of the IP block design. The Verilog code was reviewed to be sure revision handle and RTL coding instructions had been adhered to. an analogous assessment turned into conducted to make sure the verification environments at module and device level were acceptable to test the functionality of those designs. The RTL turned into validated on a FPGA device and checks had been performed on the equipment stage to check the peripherals connected to the 8051 CPU.

The IP framework as discussed during this paper is suitable for implementation in an educational centre wishing to carry out a reusable IP programme. this system and reuse concepts are commonplace in trade, however because of funding and resource constraints, may additionally now not all the time be handy to install in an tutorial atmosphere. This paper discusses the implementation of IP construction for lower bandwidth peripherals; having said that the underlying concepts of IP use and reuse are the equal.

four.1 tutorial Centre Specifics

group of workers necessities for analysis are in the end resourced from graduates pursing MEng and PhD degrees. inside the CSRC, personnel and educational researchers are chargeable for leading tasks and mentoring college students. The graduates need advantage building to carry them up to speed and having a structured building methodology allows deliverables to be met in a timely vogue. The advantages of IP advantage retention became another excuse for introducing the IP construction framework, as work generated on projects performed in the past would were tricky to progress once postgraduates had accomplished their research degrees. This became a crucial problem to unravel, as constructive task work carried out in the past may additionally were unnecessarily misplaced.

four.2. Future strategies

The cores may be additional stronger by using presenting a gadget C or C model as a part of the developmental stages to additional the level of abstraction and to pace up design verification and application building.

SystemVerilog is a hardware design and verification language with advanced facets meant to help users advance reusable, transaction-degree, coverage-pushed testbenches. suggestions akin to statement based mostly Verification (ABV) can be utilized to the bus protocol to display screen pin activity and the utility of insurance-pushed checks add self belief in working silicon and provide an exhaustive trying out environment. These elements introduce ideas of verification reuse.

Design for verify (DfT) is commonly excluded from the design flow in an educational environment. DfT is a extremely essential function essential for IP reuse. The IEEE 1500 ordinary for Embedded Core check (SECT) specifies a core wrapper design to accommodate DfT features. This IEEE 1500 compliant wrapper design may supply a helpful extension to the existing IP construction ranges.

5. Acknowledgements

The authors renowned the guide of the Circuits and systems analysis Centre (CSRC) in the electronic and computing device Engineering (ECE) Dept. on the university of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse commonplace v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA architecture document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "applying the OpenMORE assessment application for IP Cores," in ISQED 2000: Synopsys, Mentor images, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - purposeful Verificaton of HDL fashions", Kluwer academic Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may additionally 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/items/coreconnect/."

[9] R. Herveille, "WISHBONE gadget-on-Chip (SoC) Interconnection architecture for moveable IP Cores," OpenCores company, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "bendy, necessities-based mostly IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC stream."

[14] V. P. Nelson, "VLSI/FPGA Design and check CAD tool move in Mentor snap shots," Feb 15, 2006.


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